EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 91
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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PS015308-0404
Programmable Reload Timer Operation
Setting Timer Duration
There are three factors to consider when determining Programmable Reload Timer dura-
tion—clock frequency, clock divider ratio, and initial count value. Minimum duration of
the timer is achieved by loading
0000h
0000h
The time-out period of the PRT is returned by the following equation:
To calculate the time-out period with the above equation when using an initial value of
0000h
Minimum time-out duration is 4 times longer than the input clock period and is generated
by setting the clock divider ratio to 1:4 and the reload value to
duration is 2
setting the clock divider ratio to 1:256 and the reload value to
Single Pass Mode
In SINGLE PASS mode, when the end-of-count value,
the timer is disabled, and the PRT_EN bit resets to 0. To restart the timer, the CPU must
reenable the timer by setting the PRT_EN bit to 1. An example of a PRT operating in SIN-
GLE PASS mode is illustrated in Figure 21. Timer register information is indicated in
PRT Single Pass Mode Operation Example.
PRT Time-Out Period =
, because the timer first rolls over to
.
, enter a reload value of 65536 (
24
(16,777,216) times longer than the input clock period and is generated by
System Clock Frequency
P R E L I M I N A R Y
Clock Divider Ratio x Reload Value
0001h
FFFFh
. Maximum duration is achieved by loading
FFFFh
+ 1).
and then continues counting down to
0000h
0001h
0000h
, is reached, counting halts,
Programmable Reload Timers
Product Specification
. Maximum time-out
.
eZ80F92/eZ80F93
79
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