EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 60

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 12. Vectored Interrupt Operation
PS015308-0404
Memory
Mode
Z80 Mode
ADL Mode
ADL
Bit
0
1
{
tine would be stored at {MBASE[7:0], I[7:0],
significant byte is stored at the lower address.
When any one or more of the interrupt requests (IRQs) become active, an interrupt request
is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit inter-
rupt vector for the highest-priority interrupt is placed on the 8-bit interrupt vector bus,
IVECT[7:0]. The interrupt vector bus is internal to the eZ80F92 device and is therefore
not visible externally. The response time of the CPU to an interrupt request is a function of
the current instruction being executed as well as the number of wait states being asserted.
The interrupt vector, {I[7:0], IVECT[7:0]}, is visible on the address bus, ADDR[15:0],
when the interrupt service routine begins. The response of the CPU to a vectored interrupt
on the eZ80F92 device is explained in Vectored Interrupt Operation. Interrupt sources are
required to be active until the interrupt service routine starts. It is recommended that the
Interrupt Page Address Register (I) value be changed by the user from its default value of
00h
RST instruction addresses, and the maskable interrupt vectors.
00h
as this address can create conflicts between the nonmaskable interrupt vector, the
, I[7:0],
MADL
Bit
0
0
1Fh
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
IEF1
IEF2
The Starting Program Counter is effectively {MBASE, PC[15:0]}
Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack
The ADL mode bit remains cleared to 0
The interrupt vector address is located at {MBASE, I[7:0], IVECT[7:0]}
PC[15:0]
The ending Program Counter is effectively {MBASE, PC[15:0]}
The interrupt service routine must end with RETI
IEF1
IEF2
The Starting Program Counter is PC[23:0]
Push the 3-byte return address, PC[23:0], onto the SPL stack
The ADL mode bit remains set to 1
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}
PC[15:0]
The ending Program Counter is {00h, PC[15:0]}
The interrupt service routine must end with RETI
}. In Z80 mode, the two-byte address for the SPI interrupt service rou-
0
0
0
0
P R E L I M I N A R Y
({MBASE, I[7:0], IVECT[7:0]})
({00h, I[7:0], IVECT[7:0]})
1Eh
} and {MBASE, I[7:0],
Product Specification
eZ80F92/eZ80F93
Interrupt Controller
1Fh
}. The least-
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