EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 83

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Table 24. Chip Select x Control Register
(CS0_CTL = 00AAh, CS1_CTL = 00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h)
Chip Select x Bus Mode Control Register
The Chip Select Bus Mode register, detailed in Chip Select x Bus Mode Control Register,
configures the Chip Select for eZ80, Z80, Intel, or Motorola bus modes. Changing the bus
mode allows the eZ80F92 device to interface to peripherals based on the Z80-, Intel-, or
Motorola-style asynchronous bus interfaces. When a bus mode other than CPU is pro-
grammed for a particular Chip Select, the CSx_WAIT setting in that Chip Select Control
Register is ignored.
Bit
CS0_CTL Reset
CS1_CTL Reset
CS2_CTL Reset
CS3_CTL Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:5]
CSx_WAIT
4
CSX_IO
3
CSx_EN
[2:0]
Value Description
000
001
010
011
100
101
110
111
0
1
0
1
000
R/W
0 WAIT states are asserted when this Chip Select is active.
1 WAIT state is asserted when this Chip Select is active.
2 WAIT states are asserted when this Chip Select is active.
3 WAIT states are asserted when this Chip Select is active.
4 WAIT states are asserted when this Chip Select is active.
5 WAIT states are asserted when this Chip Select is active.
6 WAIT states are asserted when this Chip Select is active.
7 WAIT states are asserted when this Chip Select is active.
Chip Select is configured as a Memory Chip Select.
Chip Select is configured as an I/O Chip Select.
Chip Select is disabled.
Chip Select is enabled.
Reserved.
P R E L I M I N A R Y
7
1
0
0
0
R/W
6
1
0
0
0
R/W
5
1
0
0
0
R/W
4
0
0
0
0
R/W
3
1
0
0
0
Chip Selects and Wait States
Product Specification
R
2
0
0
0
0
eZ80F92/eZ80F93
R
1
0
0
0
0
R
0
0
0
0
0
71