EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 133

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
UART Modem Control Register
This register is used to control and check the modem status, as detailed in UART Modem
Control Registers (UART0_MCTL = 00C4h, UART1_MCTL = 00D4h).
Table 64. UART Modem Control Registers
(UART0_MCTL = 00C4h, UART1_MCTL = 00D4h)
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:6]
5
MDM
4
LOOP
3
OUT2
2
OUT1
Value
00b
0
1
0
1
0–1
0–1
Description
Reserved—must be 00b.
MULTIDROP mode disabled.
MULTIDROP mode enabled. See Parity Select Definition for
Multidrop Communications for parity select definitions.
LOOP BACK mode is not enabled.
LOOP BACK mode is enabled.
The UART operates in internal LOOP BACK mode. The
transmit data output port is disconnected from the internal
transmit data output and set to 1. The receive data input port
is disconnected and internal receive data is connected to
internal transmit data. The modem status input ports are
disconnected and the four bits of the modem control register
are connected as modem status inputs. The two modem
control output ports (OUT1&2) are set to their inactive state
No function in normal operation.
In LOOP BACK mode, this bit is connected to the DCD bit in
the UART Status Register.
No function in normal operation.
In LOOP BACK mode, this bit is connected to the RI bit in the
UART Status Register.
P R E L I M I N A R Y
R
7
0
R
6
0
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
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