EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 39

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 3. Register Map (Continued)
PS015308-0404
Address
(hex)
Watch-Dog Timer
0093
0094
General-Purpose Input/Output Ports
009A
009B
009C
009D
009E
009F
00A0
00A1
00A2
00A3
00A4
00A5
Chip Select/Wait State Generator
00A8
00A9
00AA
00AB
00AC
00AD
Notes:
1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer time-
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read Only if RTC registers are locked; Read/Write if RTC registers are unlocked.
4. After an external pin reset or a Watch-Dog Timer reset, the RTC Control register is reset to x0xxxx00b. After an
5. Read Only if Flash Memory is locked. Read/Write if Flash Memory is unlocked.
out reset, the Watch-Dog Timer Control register is reset to 20h.
RTC Alarm sleep-mode recovery reset, the RTC Control register is reset to x0xxxx10b.
Mnemonic
WDT_CTL
WDT_RR
PB_DR
PB_DDR
PB_ALT1
PB_ALT2
PC_DR
PC_DDR
PC_ALT1
PC_ALT2
PD_DR
PD_DDR
PD_ALT1
PD_ALT2
CS0_LBR
CS0_UBR
CS0_CTL
CS1_LBR
CS1_UBR
CS1_CTL
Name
Watch-Dog Timer Control Register
Watch-Dog Timer Reset Register
Port B Data Register
Port B Data Direction Register
Port B Alternate Register 1
Port B Alternate Register 2
Port C Data Register
Port C Data Direction Register
Port C Alternate Register 1
Port C Alternate Register 2
Port D Data Register
Port D Data Direction Register
Port D Alternate Register 1
Port D Alternate Register 2
Chip Select 0 Lower Bound Register
Chip Select 0 Upper Bound Register
Chip Select 0 Control Register
Chip Select 1 Lower Bound Register
Chip Select 1 Upper Bound Register
Chip Select 1 Control Register
P R E L I M I N A R Y
2
2
2
1
Reset
00/20
(hex)
XX
XX
XX
XX
FF
FF
FF
FF
E8
00
00
00
00
00
00
00
00
00
00
Product Specification
eZ80F92/eZ80F93
Access
CPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Register Map
Page
76
77
45
46
46
46
45
46
46
46
45
46
46
46
69
70
71
69
70
71
#
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