EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 126

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Table 55. UART Transmit Holding Registers
(UART0_THR = 00C0h, UART1_THR = 00D0h)
UART Receive Buffer Register
The bits in this register reflect the data received. If less than eight bits are programmed for
receive, the lower bits of the byte reflect the bits received whereas upper unused bits are 0.
The receive FIFO is mapped at this address. If the FIFO is disabled, this buffer is only one
byte deep.
These registers share the same address space as the UARTx_THR and UARTx_BRG_L
registers. See UART Receive Buffer Registers (UART0_RBR = 00C0h, UART1_RBR =
00 D0h).
Table 56. UART Receive Buffer Registers
(UART0_RBR = 00C0h, UART1_RBR = 00 D0h)
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:0]
T
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
R
x
x
D
D
Value
00h–
FFh
Value
00h–
FFh
Description
Transmit data byte.
Description
Receive data byte.
W
P R E L I M I N A R Y
X
X
R
7
7
W
R
6
X
6
X
W
R
X
X
5
5
Universal Asynchronous Receiver/Transmitter
W
R
X
X
4
4
W
R
X
X
3
3
Product Specification
W
R
X
X
2
2
eZ80F92/eZ80F93
W
X
X
R
1
1
W
X
X
R
0
0
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