EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 153

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
SPI Transmit Shift Register
The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data onto
the SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly
into the shift register for transmission. A Write to this register within an SPI device config-
ured as a master initiates transmission of the byte of the data loaded into the register. At
the completion of transmitting a byte of data, the SPIF status bit (SPI_SR[7]) is set to 1 in
both the master and slave devices.
The SPI Transmit Shift Write Only register shares the same address space as the SPI
Receive Buffer Read Only register. See SPI Transmit Shift Register (SPI_TSR = 00BCh).
Table 77. SPI Transmit Shift Register (SPI_TSR = 00BCh)
SPI Receive Buffer Register
The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive data from
the serial bus. The SPIF bit must be cleared prior to a second transfer of data from the shift
register or an overrun condition exists. In cases of overrun the byte that caused the overrun
is lost.
The SPI Receive Buffer Read Only register shares the same address space as the SPI
Transmit Shift Write Only register. See SPI Receive Buffer Register (SPI_RBR = 00BCh).
Table 78. SPI Receive Buffer Register (SPI_RBR = 00BCh)
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:0]
TX_DATA
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
RX_DATA
Value Description
00h–
FFh
Value Description
00h–
FFh
W
SPI transmit data.
SPI received data.
P R E L I M I N A R Y
X
X
R
7
7
W
R
6
X
6
X
W
R
X
X
5
5
W
R
X
X
4
4
W
R
X
X
3
3
Product Specification
Serial Peripheral Interface
W
R
X
X
2
2
eZ80F92/eZ80F93
W
X
X
R
1
1
W
X
X
R
0
0
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