EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 187

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Table 97. ZDI BREAK Control Register
(ZDI_BRK_CTL = 10h in the ZDI Write Only Register Address Space)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
brk_next
6
brk_addr3
5
brk_addr2
4
brk_addr1
3
brk_addr0
Value Description
0
1
0
1
0
1
0
1
0
1
W
P R E L I M I N A R Y
7
0
The ZDI BREAK on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
The ZDI BREAK on the next CPU instruction is enabled.
The CPU can use multibyte Op Codes and multibyte
operands. BREAK points only occur on the first Op Code
in a multibyte Op Code instruction. If the ZCL pin is High
and the ZDA pin is Low at the end of RESET, this bit is set
to 1 and a BREAK occurs on the first instruction following
the RESET. This bit is set automatically during ZDI
BREAK on address match. A BREAK can also be forced
by writing a 1 to this bit.
The ZDI BREAK, upon matching BREAK address 3, is
disabled.
The ZDI BREAK, upon matching BREAK address 3, is
enabled.
The ZDI BREAK, upon matching BREAK address 2, is
disabled.
The ZDI BREAK, upon matching BREAK address 2, is
enabled.
The ZDI BREAK, upon matching BREAK address 1, is
disabled.
The ZDI BREAK, upon matching BREAK address 1, is
enabled.
The ZDI BREAK, upon matching BREAK address 0, is
disabled.
The ZDI BREAK, upon matching BREAK address 0, is
enabled.
W
6
0
W
5
0
W
4
0
W
3
0
Product Specification
W
ZiLOG Debug Interface
2
0
eZ80F92/eZ80F93
W
1
0
W
0
0
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