EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 116

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Real-Time Clock Alarm Control Register
This register contains alarm enable bits for the Real-Time Clock. The RTC_ACTRL regis-
ter is cleared by a RESET. See Real-Time Clock Alarm Control Register (RTC_ACTRL =
00ECh).
Table 51. Real-Time Clock Alarm Control Register (RTC_ACTRL = 00ECh)
Real-Time Clock Control Register
This register contains control and status bits for the Real-Time Clock. Some bits in the
RTC_CTRL register are cleared by a RESET. The ALARM flag and associated interrupt
(if INT_EN is enabled) are cleared by reading this register. The ALARM flag is updated
by clearing (locking) the RTC_UNLOCK bit or by an increment of the RTC count. Writ-
ing to the RTC_CTRL register also resets the RTC count prescaler allowing the RTC to be
synchronized to another time source.
SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP
mode. This bit can be checked after RESET to determine if a sleep-mode recovery is
caused by the RTC. SLP_WAKE is cleared by a Read of the RTC_CTRL register.
Setting BCD_EN causes the RTC to use BCD counting in all registers including the alarm
set points.
Bit
Reset
CPU Access
Note: X = Unchanged by RESET; R/W = Read/Write; R = Read Only.
Bit
Position
[7:4]
3
ADOW_EN
2
AHRS_EN
1
AMIN_EN
0
ASEC_EN
Value Description
0000
0
1
0
1
0
1
0
1
Reserved.
The day-of-the-week alarm is disabled.
The day-of-the-week alarm is enabled.
The hours alarm is disabled.
The hours alarm is enabled.
The minutes alarm is disabled.
The minutes alarm is enabled.
The seconds alarm is disabled.
The seconds alarm is enabled.
P R E L I M I N A R Y
R
7
0
R
6
0
R
5
0
R
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
Real-Time Clock
R/W
1
0
R/W
0
0
104