EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 141

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Receiver Frequency Divider
Table 68. IrDA Physical Layer 1.4 Pulse Durations Specifications
The IrDA receiver uses a 6-bit frequency divider. The value is derived from the system
clock to measure IR_RxD pulses. The IrDA endec detects pulses that are within the IrDA
Physical Layer specified minimum and maximum ranges, with system clock frequencies
from 5 MHz up to 50 MHz.
The upper four bits of the frequency divider factor are set via the FREQ_DIV bit in the
IR_CTL register, based on the following equation:
The remaining lower two bits of the divider are set to
sponds to a period of 1.2 seconds. The FREQ_DIV value must be rounded to the nearest
integer and the resulting period of the 6-bit frequency divider must not be larger than 1.4
seconds, which is the IrDA defined minimum pulse width. If the period is greater than 1.4
seconds, FREQ_DIV should be rounded to the next lower integer. The receiver frequency
divider value versus the system clock frequency is shown in Table 2, below.
Table 69. Frequency Divider Values
Frequency Divider Factor =
System Clock
< 5.0 MHz
5.0–7.8 MHz
7.8–10.8 MHz
10.8–13.6 MHz
13.6–25 MHz
25–50 MHz
Note: *The frequency divider is disabled when set to 00h.
Baud Rate
115200
57600
FREQ_DIV
00h*
01h
02h
03h
FLOOR[4-bit Frequency Divider Factor]
ROUND[4-bit Frequency Divider Factor]
Minimum Pulse
P R E L I M I N A R Y
Width
1.41 s
1.41 s
System Clock Frequency (MHz)
Target Frequency of 3.33 MHz
Maximum Pulse
Width
4.34 s
2.23 s
03h
. The target frequency corre-
Product Specification
Infrared Encoder/Decoder
eZ80F92/eZ80F93
129