EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 149

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Data Transfer Procedure with SPI Configured as a Slave
SPI Registers
4. Assert the ENABLE pin of the slave device using a GPIO pin.
5. Load the SPI Transmit Shift Register, SPI_TSR.
6. When the SPI data transfer is complete, deassert the ENABLE pin of the slave device.
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while the SPI
3. Wait for the external SPI Master device to initiate the data transfer by asserting SS.
There are six registers in the Serial Peripheral Interface which provide control, status, and
data storage functions. The SPI registers are described in the following paragraphs.
SPI Baud Rate Generator Registers—Low Byte and High Byte
These registers hold the Low and High bytes of the 16-bit divisor count loaded by the pro-
cessor for baud rate generation. The 16-bit clock divisor value is returned by
{SPI_BRG_H, SPI_BRG_L}. Upon RESET, the 16-bit BRG divisor value resets to
0002h
FFFFh
0004h
A Write to either the Low or High byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter and the count restarted. See Tables 73 and 74.
Table 73. SPI Baud Rate Generator Register—Low Byte
(SPI_BRG_L = 00B8h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPI_BRG_L
slave is currently receiving data.
. When configured as a Master, the 16-bit divisor value must be between
, inclusive. When configured as a Slave, the 16-bit divisor value must be between
and
FFFFh
Value
00h–
FFh
, inclusive.
R/W
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
P R E L I M I N A R Y
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Product Specification
Serial Peripheral Interface
R/W
2
0
eZ80F92/eZ80F93
R/W
1
1
0003h
R/W
0
0
and
137