EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 134

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
UART Line Status Register
This register is used to show the status of UART interrupts and registers. See UART Line
Status Registers (UART0_LSR = 00C5h, UART1_LSR = 00 D5h).
Table 65. UART Line Status Registers
(UART0_LSR = 00C5h, UART1_LSR = 00 D5h)
Bit
Position
1
RTS
0
DTR
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
7
ERR
6
TEMT
Value
0–1
0–1
Value
0
1
0
1
Description
Request To Send
In normal operation, the RTS output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the CTS bit
in the UART Status Register.
Data Terminal Ready
In normal operation, the DTR output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the DSR bit
in the UART Status Register.
Description
Always 0 when operating in with the FIFO disabled. With the
FIFO enabled, this bit is reset when the UARTx_LSR register
is read and there are no more bytes with error status in the
FIFO.
Error detected in the FIFO. There is at least 1 parity, framing
or break indication error in the FIFO.
Transmit holding register/FIFO is not empty or transmit shift
register is not empty or transmitter is not idle.
Transmit holding register/FIFO and transmit shift register are
empty; and the transmitter is idle. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
P R E L I M I N A R Y
R
7
0
R
6
1
R
5
1
Universal Asynchronous Receiver/Transmitter
R
4
0
R
3
0
Product Specification
R
2
0
eZ80F92/eZ80F93
R
1
0
R
0
0
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