EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 169

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
set to 1, the I
GCE bit (I2C_SAR[0]) is set to 1.
When the Master Mode Start bit (STA) is set to 1, the I
sends a START condition on the bus when the bus is free. If the STA bit is set to 1 when
the I
repeated START condition is sent. If the STA bit is set to 1 when the I
accessed in SLAVE mode, the I
enters MASTER mode when the bus is released. The STA bit is automatically cleared after
a START condition is set. Writing a 0 to this bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I
as if a STOP condition is received, but no STOP condition is transmitted. If both STA and
STP bits are set, the I
and then transmit the START condition. The STP bit is cleared automatically. Writing a 0
to this bit produces no effect.
The I
I
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I
the Low period of the I
When a 0 is written to IFLG, the interrupt is cleared and the I
When the I
acknowledge clock pulse on the I
•
•
•
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If AAK is cleared to 0 in the Slave Transmitter mode, the byte in the
I2C_DR register is assumed to be the final byte. After this byte is transmitted, the I
block enter states
its slave address unless AAK is set. See I
2
C states is entered. The only state that does not set the IFLG bit is state F8h. If IFLG is
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave
address is received
The general call address is received and the General Call Enable bit in I2C_SAR is set
to 1
A data byte is received while in MASTER or SLAVE modes
2
2
C module is already in MASTER mode and one or more bytes are transmitted, then a
C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
2
C Acknowledge bit (AAK) is set to 1, an Acknowledge is sent during the
2
C responds to calls to its slave address and to the general call address if the
C8h
2
C bus. If the STP bit is set to 1 in slave move, the I
2
, then returns to the idle state. The I
C block first transmits the STOP condition (if in MASTER mode)
2
C bus clock line is stretched and the data transfer is suspended.
P R E L I M I N A R Y
2
C completes the data transfer in SLAVE mode and then
2
C bus if:
2
C Control Registers (I2C_CTL = 00CBh).
2
C enters MASTER mode and
2
C module does not respond to
2
C clock line is released.
Product Specification
I2C Serial I/O Interface
eZ80F92/eZ80F93
2
2
C block is being
C module operates
2
C
2
C,
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