EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 143
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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PS015308-0404
Infrared Encoder/Decoder Register
After a RESET, the Infrared Encoder/Decoder register is set to its default value. Any
writes to unused register bits are ignored and reads return a value of 0. The IR_CTL regis-
ter is described in Infrared Encoder/Decoder Control Registers (IR_CTL = 00BFh).
Table 71. Infrared Encoder/Decoder Control Registers (IR_CTL = 00BFh)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:3]
2
LOOP_BACK
1
IR_RxEN
0
IR_EN
Value
000000 Reserved.
0
1
0
1
0
1
R/W
Description
Internal LOOP BACK mode is disabled.
Internal LOOP BACK mode is enabled.
IR_TxD output is inverted and connected to IR_RxD input for
internal loop back testing.
IR_RxD data is ignored.
IR_RxD data is passed to UART0
IrDA endec is disabled.
IrDA endec is enabled.
P R E L I M I N A R Y
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R
x
Product Specification
D
.
Infrared Encoder/Decoder
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
131
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