EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 74

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Intel Bus Mode (Multiplexed Address and Data Bus)
During Read operations with multiplexed address and data, the Intel
4 states (T1, T2, T3, and T4) as described in Intel Bus Mode Read States (Multiplexed
Address and Data Bus).
Table 18. Intel Bus Mode Read States (Multiplexed Address and Data Bus)
During Write operations with multiplexed address and data, the Intel
employs 4 states (T1, T2, T3, and T4) as described in Intel Bus Mode Write States (Multi-
plexed Address and Data Bus).
Table 19. Intel Bus Mode Write States (Multiplexed Address and Data Bus)
STATE T1
STATE T2
STATE T3
STATE T4
STATE T1
STATE T2
STATE T3
STATE T4
The Read cycle begins in State T1. The CPU drives the address onto the
DATA bus and the associated Chip Select signal is asserted. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1,
the CPU drives ALE Low to facilitate the latching of the address.
During State T2, the CPU removes the address from the DATA bus and
asserts the RD signal. Depending upon the instruction, either the MREQ
or IORQ signal is asserted.
During State T3, no bus signals are altered. If the external READY (WAIT)
pin is driven Low at least one CPU system clock cycle prior to the
beginning of State T3, additional WAIT states (T
the READY pin is driven High.
The CPU latches the Read data at the beginning of State T4. The CPU
deasserts the RD signal and completes the Intel
The Write cycle begins in State T1. The CPU drives the address onto the
DATA bus and drives the ALE signal High at the beginning of T1. During
the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
During State T2, the CPU removes the address from the DATA bus and
drives the Write data onto the DATA bus. The WR signal is asserted to
indicate a Write operation.
During State T3, no bus signals are altered. If the external READY (WAIT)
pin is driven Low at least one CPU system clock cycle prior to the
beginning of State T3, additional wait states (T
READY pin is driven High.
The CPU deasserts the Write signal at the beginning of T4 identifying the
end of the Write operation. The CPU holds the data and address buses
through the end of T4. The bus cycle is completed at the end of T4.
P R E L I M I N A R Y
WAIT
WAIT
TM
Chip Selects and Wait States
Product Specification
) are asserted until the
bus mode cycle.
TM
) are asserted until
TM
eZ80F92/eZ80F93
bus mode employs
bus mode
62