EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 54

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 6. GPIO Mode Selection (Continued)
PS015308-0404
GPIO
Mode
3
4
5
6
7
8
9
Px_ALT2
Bits7:0
0
0
0
0
1
1
1
1
1
1
1
1
GPIO Mode 1.
ten to the Port x Data register (Px_DR) is presented on the pin.
GPIO Mode 2.
tristated (high impedance). The value stored in the Port x Data register produces no effect.
As in all modes, a Read from the Port x Data register returns the pin’s value. GPIO Mode
2 is the default operating mode following a RESET.
GPIO Mode 3.
an internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN
mode, an external pull-up resistor must connect the pin to the supply voltage. Writing a 0
to the Port x Data register outputs a Low at the pin. Writing a 1 to the Port x Data register
results in high-impedance output.
GPIO Mode 4.
ture an internal pull-down to the supply ground. To employ the GPIO pin in OPEN-
SOURCE mode, an external pull-down resistor must connect the pin to the supply ground.
Writing a 1 to the Port x Data register outputs a High at the pin. Writing a 0 to the Port x
Data register results in a high-impedance output.
GPIO Mode 5.
Px_ALT1
Bits7:0
1
1
1
1
0
0
0
0
1
1
1
1
The port pin is configured as open-source I/O. The GPIO pins do not fea-
Reserved. This pin produces high-impedance output.
The port pin is configured as a standard digital output pin. The value writ-
The port pin is configured as a standard digital input pin. The output is
The port pin is configured as open-drain I/O. The GPIO pins do not feature
Px_DDR
Bits7:0
0
0
1
1
0
0
1
1
0
0
1
1
Bits7:0 Port Mode
Px_DR
P R E L I M I N A R Y
0
1
0
1
0
1
0
1
0
1
0
1
Open-drain output
Open-drain I/O
Open-source I/O
Open-source output
Reserved
Interrupt—dual edge triggered
Port B, C, or D—alternate function controls port I/O.
Port B, C, or D—alternate function controls port I/O.
Interrupt—active Low
Interrupt—active High
Interrupt—falling edge triggered High impedance
Interrupt—rising edge triggered High impedance
General-Purpose Input/Output
Product Specification
eZ80F92/eZ80F93
Output
0
High impedance
High impedance
1
High impedance
High impedance
High impedance
High impedance
42