EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 136

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
UART Modem Status Register
This register is used to show the status of the UART signals. See UART Modem Status
Registers (UART0_MSR = 00C6h, UART1_MSR = 00 D6h).
Table 66. UART Modem Status Registers
(UART0_MSR = 00C6h, UART1_MSR = 00 D6h)
Bit
Position
0
DR
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
7
DCD
6
RI
5
DSR
4
CTS
Value
0
1
Value
0–1
0–1
0–1
0–1
Description
This bit is reset to 0 when the UARTx_RBR register is read or
all bytes are read from the receiver FIFO.
Data Ready
If the FIFO is not enabled, this bit is set to 1 when a complete
incoming character is transferred into the receiver buffer
register from the receiver shift register. If the FIFO is enabled,
this bit is set to 1 when a character is received and transferred
to the receiver FIFO.
Description
Data Carrier Detect
In NORMAL mode, this bit reflects the inverted state of the
DCDx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[3] = out2.
Ring Indicator
In NORMAL mode, this bit reflects the inverted state of the RIx
input pin. In LOOP BACK mode, this bit reflects the value of
the UARTx_MCTL[2] = out1.
Data Set Ready
In NORMAL mode, this bit reflects the inverted state of the
DSRx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[0] = DTR.
Clear To Send
In NORMAL mode, this bit reflects the inverted state of the
CTSx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[1] = RTS.
P R E L I M I N A R Y
X
R
7
R
6
X
R
X
5
Universal Asynchronous Receiver/Transmitter
R
X
4
R
X
3
Product Specification
R
X
2
eZ80F92/eZ80F93
X
R
1
X
R
0
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