EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 180
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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Figure 42.ZDI Block Data Write Timing
PS015308-0404
ZDA
ZCL
ZDI Read Operations
ZDI Address
ZDI Block Write
The Block Write operation is initiated in the same manner as the single-byte Write opera-
tion, but instead of terminating the Write operation after the first data byte is transferred,
the ZDI master can continue to transmit additional bytes of data to the ZDI slave on the
eZ80F92 device. After the receipt of each byte of data the ZDI register address increments
by 1. If the ZDI register address reaches the end of the Write Only ZDI register address
space (
Block Write operations.
lsb of
ZDI Single-Byte Read
Single-byte Read operations are initiated in the same manner as single-byte Write opera-
tions, with the exception that the R/W bit of the ZDI register address is set to 1. Upon
receipt of a slave address with the R/W bit set to 1, the eZ80F92 device’s ZDI block loads
the selected data into the shifter at the beginning of the first cycle following the single-bit
data separator. The most-significant bit (msb) is shifted out first. Figure 43 illustrates the
timing for ZDI single-byte Read operations.
A0
7
30h
Write
8
Byte Separator
), the address stops incrementing. Figure 42 illustrates the timing for ZDI
Single-Bit
0/1
9
of DATA
Byte 1
msb
D7
1
P R E L I M I N A R Y
D6
2
D5
3
ZDI Data Bytes
D1
7
of DATA
Byte 1
D0
lsb
8
Byte Separator
Single-Bit
0/1
9
D7
1
Product Specification
of DATA
ZiLOG Debug Interface
Byte 2
eZ80F92/eZ80F93
msb
D6
2
1
9
168
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