EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 148
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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PS015308-0404
SPI Baud Rate Generator
Data Transfer Procedure with SPI Configured as the Master
4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI
Clearing the Mode Fault flag is performed by reading the SPI Status register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault flag is cleared.
Write Collision
The WRITE COLLISION flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made
to write to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing
the WCOL bit is performed by reading SPI_SR with the WCOL bit set.
The SPI’s Baud Rate Generator creates a lower frequency clock from the high-frequency
system clock. The Baud Rate Generator output is used as the clock source by the SPI.
Baud Rate Generator Functional Description
The SPI’s Baud Rate Generator consists of a 16-bit downcounter, two 8-bit registers, and
associated decoding logic. The Baud Rate Generator’s initial value is defined by the two
BRG Divisor Latch registers, {SPI_BRG_H, SPI_BRG_L}. At the rising edge of each
system clock, the BRG decrements until it reaches the value
clock rising edge, the BRG reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and
outputs a pulse to indicate the end-of-count. Calculate the SPI Data Rate with the follow-
ing equation:
Upon RESET, the 16-bit BRG divisor value resets to
a Master, the BRG divisor value must be set to a value of
is operating as a Slave, the BRG divisor value must be set to a value of
A software Write to either the Low- or High-byte registers for the BRG Divisor Latch
causes both the Low and High bytes to load into the BRG counter, and causes the count to
restart.
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. External device must deassert the SS pin if currently asserted.
3. Load the SPI Control Register, SPI_CTL.
SPI Data Rate (bits/s)
interrupt is generated.
=
System Clock Frequency
2 X SPI Baud Rate Generator Divisor
P R E L I M I N A R Y
0002h
0003h
. When the SPI is operating as
0001h
Product Specification
or greater. When the SPI
Serial Peripheral Interface
. On the next system
eZ80F92/eZ80F93
0004h
or greater.
136
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