EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 131

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Bit
Position
6
SB
5
FPE
4
EPS
3
PEN
[2:0]
CHAR
Note: *Receive Parity is set to SPACE in MULTIDROP mode.
Value
0
1
0
1
0
1
0
1
000–
111
Description
Do not send a BREAK signal.
Send Break
UART sends continuous zeroes on the transmit output from
the next bit boundary. The transmit data in the transmit shift
register is ignored. After forcing this bit High, the
is 0 only after the bit boundary is reached. Just before forcing
T
to the transmit FIFO during a break should be written only
after the THRE bit of UARTx_LSR register goes High. This
new data is transmitted after the UART recovers from the
break. After the break is removed, the UART recovers from
the break for the next BRG edge.
Do not force a parity error.
Force a parity error. When this bit and the party enable bit
(PEN) are both 1, an incorrect parity bit is transmitted with the
data byte.
Use odd parity for transmit and receive. The total number of 1
bits in the transmit data plus parity bit is odd. Use as a SPACE
bit in MULTIDROP mode. See Parity Select Definition for
Multidrop Communications for parity select definitions.*
Use even parity for transmit and receive. The total number of
1 bits in the transmit data plus parity bit is even. Use as a
MARK bit in MULTIDROP mode. See Parity Select Definition
for Multidrop Communications for parity select definitions.
Parity bit transmit and receive is disabled.
Parity bit transmit and receive is enabled. For transmit, a
parity bit is generated and transmitted with every data
character. For receive, the parity is checked for every
incoming data character. In MULTIDROP mode, receive
parity is checked for space parity.
UART Character Parameter Selection—see UART Character
Parameter Definition for a description of the values.
P R E L I M I N A R Y
x
D
to 0, the transmit FIFO is cleared. Any new data written
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80F92/eZ80F93
T
x
D
output
119