EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 66

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Figure 8.Example: Wait State Operation Read Operation
PS015308-0404
ADDR[23:0]
Chip Selects During Bus Request/Bus Acknowledge Cycles
DATA[7:0]
INSTRD
(output)
MREQ
CSx
X
RD
IN
An example of WAIT state operation is illustrated in Figure 8. In this example, the Chip
Select is configured to provide a single WAIT state. The external peripheral being
accessed drives the WAIT pin Low to request assertion of an additional WAIT state. If the
WAIT pin is asserted for additional system clock cycles, WAIT states are added until the
WAIT pin is deasserted (High).
When the CPU relinquishes the address bus to an external peripheral in response to an
external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The
external peripheral can then drive the address bus (and data bus). The CPU continues to
generate Chip Select signals in response to the address on the bus. External devices cannot
access the internal registers of the eZ80F92 device.
T
CLK
P R E L I M I N A R Y
T
WAIT
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
54