EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 67

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 14.
PS015308-0404
STATE T1
STATE T2
STATE T3
Bus Mode Controller
eZ80 Bus Mode
Z80 Bus Mode
Z80
The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated Chip Select signal is asserted.
During State T2, the RD signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional WAIT states (T
asserted until the WAIT pin is driven High.
During State T3, no bus signals are altered. The data is latched by the eZ80F92 device at
the rising edge of the CPU system clock at the end of State T3.
Bus Mode Read States
The bus mode controller allows the address and data bus timing and signal formats of the
eZ80F92 device to be configured to connect seamlessly with external eZ80
or Motorola-compatible devices. Bus modes for each of the chip selects can be configured
independently using the Chip Select Bus Mode Control Registers. The number of CPU
system clock cycles per bus mode state is also independently programmable. For Intel bus
mode, multiplexed address and data can be selected in which the lower byte of the address
and the data byte both use the data bus, DATA[7:0]. Each of the bus modes is explained in
more detail in the following sections.
Chip selects configured for eZ80 bus mode do not modify the bus signals from the CPU.
The timing diagrams for external Memory and I/O Read and Write operations are shown
in the AC Characteristics section on page 233. The default mode for each chip select is
eZ80 mode.
Chip selects configured for Z80 mode modify the CPU bus signals to match the Z80
microprocessor address and data bus interface signal format and timing. During read oper-
ations, the Z80 bus mode employs three states (T1, T2, and T3) as described in Z80 Bus
Mode Read States.
During Write operations, Z80 bus mode employs 3 states (T1, T2, and T3) as described in
Z80 Bus Mode Write States.
P R E L I M I N A R Y
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
WAIT
®
, Z80-, Intel-,
) are
55