EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 251

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Wait State Timing for Read Operations
Table 152. External I/O Write Timing (Continued)
Figure 61 illustrates the extension of the memory access signals using a single WAIT state
for a Read operation. This WAIT state is generated by setting CS_WAIT to
Chip Select Control Register.
Figure 61.Wait State Timing for Read Operations
Parameter
T
T
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to
ADDR[23:0]
9
10
DATA[7:0]
INSTRD
(output)
MREQ
ADDR, DATA, CSx, or IORQ.
CSx
X
RD
IN
Abbreviation
Clock Fall to WR Assertion Delay
Clock Rise to WR Deassertion Delay*
WR Deassertion to ADDR Hold Time
WR Deassertion to DATA Hold Time
WR Deassertion to CSx Hold Time
WR Deassertion to IORQ Hold Time
T
CLK
P R E L I M I N A R Y
T
WAIT
Product Specification
0.25
0.25
0.25
0.25
Min
Electrical Characteristics
1.8
1.6
eZ80F92/eZ80F93
Delay (ns)
001h
Max
6.5
6.5
in the
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—
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