EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 214
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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PS015308-0404
Table 115. Flash Data Register (FLASH_DATA = 00F6h)
Flash Address Upper Byte Register
The FLASH_ADDR_U register defines the upper 7 bits of the address for Flash memory.
Changing the value of FLASH_ADDR_U allows the on-chip 128 KB/64 KB Flash mem-
ory to be mapped to any location within the 16 MB linear address space of the eZ80F92
device. If the on-chip Flash memory is enabled, Flash address assumes priority over any
external Chip Selects. The external Chip Select signals are not asserted if the correspond-
ing Flash address is enabled. The internal Flash memory does not hold priority over inter-
nal SRAM.
Table 116. Flash Address Upper Byte Register (FLASH_ADDR_U = 00F7h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
FLASH_DATA
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:1]
FLASH_ADDR_U
0
Value Description
00h–
FFh
Value Description
00h–
FEh
0
R/W
Data value to be written to Flash during an I/O Write
operation.
R/W
P R E L I M I N A R Y
X
7
7
0
These bits define the upper byte of the Flash address. When
on-chip Flash is enabled, the Flash address space begins at
address {FLASH_ADDR_U, 0b, 0000h}. On-chip Flash is
prioritized over all external Chip Selects.
Reserved (enforces alignment on a 128 KB boundary).
R/W
R/W
6
X
6
0
R/W
R/W
X
5
5
0
R/W
R/W
X
4
4
0
R/W
R/W
X
3
3
0
Product Specification
R/W
R/W
X
2
2
0
eZ80F92/eZ80F93
R/W
R/W
X
1
1
0
Flash Memory
R/W
X
R
0
0
0
202
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