EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 130

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
UART Line Control Register
This register is used to control the communication control parameters. See Tables 61 and
62.
Table 61. UART Line Control Registers
(UART0_LCTL = 00C3h, UART1_LCTL = 00D3h)
Bit
Position
2
CLRTXF
1
CLRRXF
0
FIFOEN
Note: *Receive FIFO is not enabled during
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
DLAB
Note: *Receive Parity is set to SPACE in MULTIDROP mode.
Value
0
1
0
1
0
1
Value
0
1
Description
No effect.
Clear the transmit FIFO and reset the transmit FIFO pointer.
Valid only if the FIFO is enabled.
No effect.
Clear the receive FIFO, clear the receive error FIFO, and
reset the receive FIFO pointer. Valid only if the FIFO is
enabled.
Transmit and receive FIFOs are disabled. Transmit and
receive buffers are only 1 byte deep.
Transmit and receive FIFOs are enabled*.
R/W
Description
Access to the UART registers at I/O addresses UARTx_RBR,
UARTx_THR, and UARTx_IER is enabled.
Access to the Baud Rate Generator registers at I/O addresses
UARTx_BRG_L and UARTx_BRG_H is enabled.
P R E L I M I N A R Y
7
0
R/W
6
0
MULTIDROP
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
mode.
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
118