EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 78

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 20. Motorola Bus Mode Read States (Continued)
Table 21. Motorola Bus Mode Write States
PS015308-0404
STATE S4
STATE S5
STATE S6
STATE S7
STATE S0
STATE S1
STATE S2
STATE S3
STATE S4
STATE S5
STATE S6
STATE S7
During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
signal. If the termination signal is not asserted at least one full CPU clock period prior to
the rising clock edge at the end of S4, the CPU inserts WAIT (T
asserted. Each WAIT state is a full bus mode cycle.
During state S5, no bus signals are altered.
During state S6, data from the external peripheral device is driven onto the data bus.
On the rising edge of the clock entering state S7, the CPU latches data from the
addressed peripheral device and deasserts AS and DS. The peripheral device deasserts
DTACK at this time.
The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves
R/W Low).
Entering S1, the CPU drives a valid address on the address bus.
On the rising edge of S2, the CPU asserts AS and drives R/W Low.
During S3, the data bus is driven out of the high-impedance state as the data to be written
is placed on the bus.
At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal
DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period
prior to the rising clock edge at the end of S4, the CPU inserts WAIT (T
DTACK is asserted. Each WAIT state is a full bus mode cycle.
During S5, no bus signals are altered.
During S6, no bus signals are altered.
Upon entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the
CPU drives R/W High. The peripheral device deasserts DTACK at this time.
The eight states for a Write operation in Motorola bus mode are described in Motorola Bus
Mode Write States.
P R E L I M I N A R Y
WAIT
Chip Selects and Wait States
Product Specification
) states until DTACK is
eZ80F92/eZ80F93
WAIT
) states until
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