EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 22

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)
PS015308-0404
Pin #
37
38
39
40
41
42
43
44
45
46
Symbol
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
V
V
IORQ
MREQ
DD
SS
Function
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Power Supply
Ground
Input/Output
Request
Memory
Request
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional, Active
Low
Bidirectional, Active
Low
P R E L I M I N A R Y
Description
The data bus transfers data to and from I/O
and memory devices. The CPU drives
these lines only during Write cycles when
the CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives
these lines only during Write cycles when
the CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives
these lines only during Write cycles when
the CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives
these lines only during Write cycles when
the CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives
these lines only during Write cycles when
the CPU is the bus master.
The data bus transfers data to and from I/O
and memory devices. The CPU drives
these lines only during Write cycles when
the CPU is the bus master.
Power Supply.
Ground.
IORQ indicates that the CPU is accessing
a location in I/O space. RD and WR
indicate the type of access. The CPU does
not drive this line during RESET. It is an
input in bus acknowledge cycles.
MREQ Low indicates that the CPU is
accessing a location in memory. The RD,
WR, and INSTRD signals indicate the type
of access. The CPU does not drive this line
during RESET. It is an input in bus
acknowledge cycles.
Product Specification
eZ80F92/eZ80F93
Architectural Overview
10