EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 68

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 15.
Figure 9.Example: Z80 Bus Mode Read Timing
PS015308-0404
STATE T1
STATE T2
STATE T3
Z80
The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated Chip Select signal is asserted.
During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one CPU
system clock cycle prior to the end of State T2, additional WAIT states (T
asserted until the WAIT pin is driven High.
During State T3, no bus signals are altered.
Bus Mode Write States
Z80 bus mode Read and Write timing is illustrated in Figures 9 and 10 . The Z80 bus mode
states can be configured for 1 to 15 CPU system clock cycles. In the figures, each Z80 bus
mode state is two CPU system clock cycles in duration. Figures 9 and 10 also illustrate
the assertion of 1 wait state (T
cycle.
System Clock
ADDR[23:0]
DATA[7:0]
or IORQ
MREQ
WAIT
CSx
WR
RD
P R E L I M I N A R Y
T1
WAIT
) by the external peripheral during each Z80 bus mode
T2
T
CLK
T3
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
WAIT
) are
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