EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 55

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Note:
GPIO Mode 6.
falling edge on the pin cause an interrupt request to be sent to the CPU. Writing a 1 to the
Port x Data register bit position resets the corresponding interrupt request. Writing a 0 pro-
duces no effect. The programmer must set the Port x Data register before entering the
edge-triggered interrupt mode.
GPIO Mode 7.
alternate (secondary) functions assigned to the pin. For example, the alternate mode func-
tion for PC7 is RI1 and the alternate mode function for PB4 is the Timer 4 Out. When
GPIO Mode 7 is enabled, the pin output data and pin tristated control come from the alter-
nate function's data output and tristate control, respectively. The value in the Port x Data
register produces no effect on operation.
GPIO Mode 8.
request is generated when the level at the pin is the same as the level stored in the Port x
Data register. The port pin value is sampled by the system clock. The input pin must be
held at the selected interrupt level for a minimum of 2 clock periods to initiate an interrupt.
The interrupt request remains active as long as this condition is maintained at the external
source.
GPIO Mode 9.
value in the Port x Data register determines if a positive or negative edge causes an inter-
rupt request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges. The interrupt request remains active until a 1 is writ-
ten to the corresponding interrupt request of the Port x Data register bit. Writing a 0 pro-
duces no effect on operation. The programmer must set the Port x Data register before
entering the edge-triggered interrupt mode.
A simplified block diagram of a GPIO port pin is illustrated in Figure 5.
Input signals are sampled by the system clock before being passed to the alternate
function input.
This bit enables a dual edge-triggered interrupt mode. Both a rising and a
For Ports B, C, and D, the port pin is configured to pass control over to the
The port pin is configured for level-sensitive interrupt modes. An interrupt
The port pin is configured for single edge-triggered interrupt mode. The
P R E L I M I N A R Y
General-Purpose Input/Output
Product Specification
eZ80F92/eZ80F93
43