EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 125

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
UART Registers
Table 54. UART Baud Rate Generator Register—High Bytes
(UART0_BRG_H = 00C1h, UART1_BRG_H = 00D1h)
After a RESET, all UART registers are set to their default values. Any writes to unused
registers or register bits are ignored and reads return a value of 0. For compatibility with
future revisions, unused bits within a register should always be written with a value of 0.
Read/Write attributes, reset conditions, and bit descriptions of all of the UART registers
are provided in this section.
UART Transmit Holding Register
If less than eight bits are programmed for transmission, the lower bits of the byte written
to this register are selected for transmission. The transmit FIFO is mapped at this address.
The user can write up to 16 bytes for transmission at one time to this address if the FIFO is
enabled by the application. If the FIFO is disabled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and UARTx_BRG_L
registers. See UART Transmit Holding Registers (UART0_THR = 00C0h, UART1_THR
= 00D0h).
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:0]
UART_BRG_H
Value
00h–
FFh
R/W
Description
These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UART_BRG_H, UART_BRG_L}.
P R E L I M I N A R Y
7
0
R/W
6
0
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
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