EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 254

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
External Bus Acknowledge Timing
External System Clock Driver (PHI) Timing
Bus Acknowledge Timing provides information on the bus acknowledge timing. Once the
external bus master detects BUSACK asserted and drives IORQN, MREQN, A[23:0] there
is an asynchronous prop delay to the CS[3:0] outputs being valid.
Table 154. Bus Acknowledge Timing
PHI System Clock Timing provides timing information for the PHI pin. The PHI pin
allows external peripherals to synchronize with the internal system clock driver on the
eZ80F92 device.
Table 155. PHI System Clock Timing
Parameter
T
T
T
Parameter
T
T
1
2
3
1
2
Abbreviation
Clock Rise to BUSACK Assertion Delay
Clock Rise to BUSACK Deassertion Delay
IORQN, MREQN, A[23:0] input to CS[3:0]
output prop delay
Abbreviation
Clock (XIN) Rise to PHI Rise
Clock (XIN) Fall to PHI Fall
P R E L I M I N A R Y
Product Specification
Min
Min
Electrical Characteristics
2.0
2.0
—
—
—
eZ80F92/eZ80F93
Delay (ns)
Delay (ns)
Max
14.0
14.0
10.0
Max
6.0
6.0
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