EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 71

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Table 16. Intel Bus Mode Read States (Separate Address and Data Buses)
During Write operations with separate address and data buses, the Intel bus mode employs
4 states (T1, T2, T3, and T4) as described in Intel Bus Mode Write States (Separate
Address and Data Buses).
Table 17. Intel Bus Mode Write States (Separate Address and Data Buses)
Intel bus mode timing is illustrated for a Read operation in Figure 12 and for a Write oper-
ation in Figure 13. If the READY signal (external WAIT pin) is driven Low prior to the
beginning of State T3, additional wait states (T
is driven High. The Intel bus mode states can be configured for 2 to 15 CPU system clock
cycles. In the figures, each Intel
tion. Figures 12 and 13 also illustrate the assertion of one WAIT state (T
selected peripheral.
STATE T3
STATE T4
STATE T1
STATE T2
STATE T3
STATE T4
During State T3, no bus signals are altered. If the external READY (WAIT)
pin is driven Low at least one CPU system clock cycle prior to the
beginning of State T3, additional wait states (T
READY pin is driven High.
The CPU latches the Read data at the beginning of State T4. The CPU
deasserts the RD signal and completes the Intel bus mode cycle.
The Write cycle begins in State T1. The CPU drives the address onto the
address bus, the associated Chip Select signal is asserted, and the data
is driven onto the data bus. The CPU drives the ALE signal High at the
beginning of T1. During the middle of T1, the CPU drives ALE Low to
facilitate the latching of the address.
During State T2, the CPU asserts the WR signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
During State T3, no bus signals are altered. If the external READY (WAIT)
pin is driven Low at least one CPU system clock cycle prior to the
beginning of State T3, additional WAIT states (T
the READY pin is driven High.
The CPU deasserts the WR signal at the beginning of State T4. The CPU
holds the data and address buses through the end of T4. The bus cycle is
completed at the end of T4.
P R E L I M I N A R Y
TM
bus mode state is 2 CPU system clock cycles in dura-
WAIT
) are asserted until the READY signal
WAIT
WAIT
Chip Selects and Wait States
Product Specification
) are asserted until the
) are asserted until
eZ80F92/eZ80F93
WAIT
) by the
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