EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 177

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

eZ80F92/eZ80F93
Product Specification
165
only available when the On-Chip Instrumentation is disabled and the ZDI is therefore
enabled. For general data communication, the data value on the ZDA pin can change only
when ZCL is Low (0). The only exception is the ZDI START bit, which is indicated by a
High-to-Low transition (falling edge) on the ZDA pin while ZCL is High.
Data is shifted into and out of ZDI, with the most-significant bit (bit 7) of each byte being
first in time, and the least-significant bit (bit 0) last in time. All information is passed
between the master and the slave in 8-bit (single-byte) units. Each byte is transferred with
nine clock cycles: eight to shift the data, and the ninth for internal operations.
ZDI START Condition
All ZDI commands are preceded by the ZDI START signal, which is a High-to-Low tran-
sition of ZDA when ZCL is High. The ZDI slave on the eZ80F92 device continually mon-
itors the ZDA and ZCL lines for the START signal and does not respond to any command
until this condition is met. The master pulls ZDA Low, with ZCL High, to indicate the
beginning of a data transfer with the ZDI block. Figures 38 and 39 illustrate a valid ZDI
START signal prior to writing and reading data, respectively. A Low-to-High transition of
ZDA while the ZCL is High yields no effect.
Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as illustrated
in Figure 38. Data is shifted out during a Read from the ZDI block on the falling edge of
ZCL as illustrated in Figure 39. When an operation is completed, the master stops during
the ninth cycle and holds the ZCL signal High.
ZDI Data In
ZDI Data In
(Write)
(Write)
ZCL
ZDA
Start Signal
Figure 38.ZDI Write Timing
PS015308-0404
P R E L I M I N A R Y
ZiLOG Debug Interface