EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 137

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
UART Scratch Pad Register
The UARTx_SPR register can be used by the system as a general-purpose Read/Write reg-
ister. See UART Scratch Pad Registers (UART0_SPR = 00C7h, UART1_SPR = 00D7h).
Table 67. UART Scratch Pad Registers
(UART0_SPR = 00C7h, UART1_SPR = 00D7h)
Bit
Position
3
DDCD
2
TERI
1
DDSR
0
DCTS
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPR
Value
0–1
0–1
0–1
0–1
Value
00h–
FFh
Description
Delta Status Change of DCD
This bit is set to 1 whenever the DCDx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Trailing Edge Change on RI
This bit is set to 1 whenever a falling edge is detected on the
RIx pin. This bit is reset to 0 when the UARTx_MSR register is
read.
Delta Status Change of DSR
This bit is set to 1 whenever the DSRx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Delta Status Change of CTS
This bit is set to 1 whenever the CTSx pin changes state.
This bit is reset to 0 when the UARTx_MSR register is read.
R/W
Description
The UART scratch pad register is available for use as a
general-purpose Read/Write register.
P R E L I M I N A R Y
7
0
R/W
6
0
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
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