EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 57

MODULE EZ80F92 512K 20MHZ

EZ80F920120MOD

Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog

Specifications of EZ80F920120MOD

Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
PS015308-0404
GPIO Control Registers
interrupt, writing a 1 to that pin’s Port x Data register causes a reset of the edge-detected
interrupt. The programmer must set the bit in the Port x Data register to 1 before entering
either single or dual edge-triggered interrupt mode for that port pin.
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising and
a falling edge on the pin cause an interrupt request to be sent to the CPU.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port x Data register determines if a positive or negative edge causes an interrupt
request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges.
The 12 GPIO Control Registers operate in groups of four with a set for each Port (B, C,
and D). Each GPIO port features a Port Data register, Port Data Direction register, Port
Alternate register 1, and Port Alternate register 2.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to the Port
x Data registers, detailed in Port x Data Registers (PB_DR = 009Ah, PC_DR = 009Eh,
PD_DR = 00A2h), are driven on the corresponding pins. In all modes, reading from the
Port x Data registers always returns the current sampled value of the corresponding pins.
When the port pins are configured as edge-triggered interrupt sources, writing a 1 to the
corresponding bit in the Port x Data register clears the interrupt signal that is sent to the
CPU. When the port pins are configured for edge-selectable interrupts or level-sensitive
interrupts, the value written to the Port x Data register bit selects the interrupt edge or
interrupt level. See
Table 7. Port x Data Registers (PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h)
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
GPIO Mode Selection
R/W
P R E L I M I N A R Y
X
7
R/W
6
X
for more information.
R/W
X
5
R/W
X
4
R/W
X
3
General-Purpose Input/Output
Product Specification
R/W
X
2
eZ80F92/eZ80F93
R/W
X
1
R/W
X
0
45

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