EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 262

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Flash Memory Overview 197
framing error 106, 108, 115
full-duplex transmission 135
Functional Description, Infrared Encoder/Decoder
G
General-Purpose Input/Output 41
GND—see Ground
GPIO—see General-Purpose Input/Output
Ground 2
H
HALT instruction 37, 177, 185, 214
HALT mode 1, 11, 37–38, 227, 228, 232
HALT_SLP 11
handshake 106, 147
high-frequency system clock 136
I
I/O Chip Select Operation 25, 52
I/O space 5–10, 50, 52
I
I
I
I
I
I
I
I
PS015308-0404
2
2
2
2
2
2
2
2
C Acknowledge bit 144, 148–150, 152, 153,157
C bus 142, 146, 154
C Clock Control Register 161
C Control Register 156
C Data Register 156
C Extended Slave Address Register 155
C General Characteristics 142
C Registers 154
126
Control Registers 45
Interrupts 44
modes 42, 43
Operation 41
Overview 41
Port Input Sample Timing 241
Port Output Timing 243
port pins 34, 41, 46
Op-Code Map 216
clock 142
protocol 143
P R E L I M I N A R Y
I
I
I
I
I
I
IEEE Standard 1149.1 190–191
IEF1 48–49, 186
IEF2 48–49
IFLG bit 142, 147, 150, 152–153, 157, 159–160
IM 0, Op Code Map 219
IM 1, Op Code Map 219
IM 2, Op Code Map 219
Information Page 196–197, 200, 205, 207–209
Infrared Encoder/Decoder 39, 126, 127, 130–131,
Input/Output Request 10–11, 22, 53, 55–56, 58–59,
INSTRD—see Instruction Read
Instruction Read 11, 22
Instruction Store 4
Intel Bus Mode 55, 57
internal pull-up 42
internal system clock 53
Interrupt Controller 47
Interrupt Enable bit 11, 91, 109, 156
Interrupt Enable Flag 49, 186
interrupt input 13–16, 18–19
Interrupt Request 43–45, 47–49, 85, 206
Interrupt Service Routine 47, 49
interrupt vector 47–48
interrupt, highest-priority 47–48
interrupts, edge-selectable 45
Introduction to On-Chip Instrumentation 190
Introduction, ZiLOG Debug Interface 163
2
2
2
2
2
2
C Serial Clock 20, 24, 142–144, 161
C Serial Data 20
C Serial I/O Interface 142
C Slave Address Register 154
C Software Reset Register 162
C Status Register 159
62
Register 131
Signal Pins 130
Assertion Delay 237–238
Deassertion Delay 237–238
Hold Time 239
0 Registers 182
Multiplexed Address and Data Bus 62
Separate Address and Data Buses 58
SPI 48
address 47–49
Product Specification
eZ80F92/eZ80F93
Index
250