EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 65

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
WAIT States
WAIT Input Signal
Caution:
If all of the foregoing conditions are met to generate an I/O Chip Select, then the following
actions occur:
•
•
•
For each of the Chip Selects, programmable WAIT states can be asserted to provide exter-
nal devices with additional clock cycles to complete their Read or Write operations. The
number of WAIT states for a particular Chip Select is controlled by the 3-bit field
CSx_WAIT (CSx_CTL[7:5]). The WAIT states can be independently programmed to pro-
vide 0 to 7 WAIT states for each Chip Select. The WAIT states idle the CPU for the speci-
fied number of system clock cycles.
Similar to the programmable WAIT states, an external peripheral can drive the WAIT input
pin to force the CPU to provide additional clock cycles to complete its Read or Write oper-
ation. Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the first
rising edge of the internal system clock following deassertion of the WAIT pin.
Figure 7.Wait Input Sampling Block Diagram
The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low)
IORQ is asserted (driven Low)
Depending upon the instruction, either RD or WR is asserted (driven Low)
If the WAIT pin is to be driven by an external device, the corresponding Chip
Select for the device must be programmed to provide at least one WAIT state.
Due to input sampling of the WAIT input pin (shown in Figure 7), one program-
mable WAIT state is required to allow the external peripheral sufficient time to
assert the WAIT pin. It is recommended that the corresponding Chip Select for
the external device be programmed to provide the maximum number of WAIT
states (seven).
Wait
Pin
P R E L I M I N A R Y
System Clock
D
Q
eZ80
CPU
Chip Selects and Wait States
Product Specification
eZ80F92/eZ80F93
53