EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 164

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Note:
Table 83. I
When all bytes are received, a NACK should be sent, then the microcontroller should
write a 1 to the STP bit in the
clears the STP bit and returns to the idle state.
Slave Transmit
In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver.
The I
Read bit after a START condition. The I
bit is set to 1) and sets the IFLG bit in the I2C_CTL register and the I2C_SR register con-
tains the status code
I
ing the transmission of an address, and the slave address and Read bit are received. This
action is represented by the status code
The data byte to be transmitted is loaded into the
cleared. After the I
and the
the
Code
50h
58h
38h
2
C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur-
I2C_DR
2
C enters SLAVE TRANSMIT mode when it receives its own slave address and a
When I
register), it transmits an acknowledge after the first address byte is received after a
restart. An interrupt is generated, IFLG is set but the status does not change. No
second address byte is sent by the master. It is up to the slave to remember it had
been selected prior to the restart.
I2C_SR
I
Data byte received,
ACK transmitted
Data byte received,
NACK transmitted
Arbitration lost in
NACK bit
2
2
C Master Receive Status Codes For Data Bytes
C State
register, the AAK bit is cleared when the IFLG is cleared. After the final byte
2
C contains a 10-bit slave address (signified by
register contains
2
C transmits the byte and receives an acknowledge, the IFLG bit is set
A8h
.
P R E L I M I N A R Y
I2C_CTL
Microcontroller Response Next I
Read DATA, clear IFLG,
clear AAK = 0
Or read DATA, clear IFLG,
set AAK = 1
Read DATA, set STA,
clear IFLG
Or read DATA, set STP,
clear IFLG
Or read DATA, set
STA & STP, clear IFLG
Same as master transmit
B8h
. When the final byte to be transmitted is loaded into
register. The I
B0h
2
C then transmits an acknowledge bit (if the AAK
in the
I2C_DR
I2C_SR
2
C then transmits a STOP condition,
register and the IFLG bit
register.
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit repeated START
Transmit STOP
Transmit STOP then
START
Same as master transmit
F0h–F7h
Product Specification
2
C Action
I2C Serial I/O Interface
eZ80F92/eZ80F93
in the I2C_SAR
152