EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 139
![MODULE EZ80F92 512K 20MHZ](/photos/6/75/67554/ez80f920120mod_sml.jpg)
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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Figure 26.Infrared Data Transmission
PS015308-0404
UART_TxD
Baud Rate
Transmit
IR_TxD
Receive
7-clock
Clock
delay
endec. Refer to the Universal Asynchronous Receiver/Transmitter section on page 106 for
more information on the UART and its Baud Rate Generator.
The data to be transmitted via the IR transceiver is first sent to UART0. The UART trans-
mit signal (TxD) and Baud Rate Clock are used by the IrDA endec to generate the modu-
lation signal (IR_TxD) that drives the infrared transceiver. To enable transmit encoding,
the IR_RxEN bit in the IR_CTL register must be set to 0.
Each UART bit is 16-clocks wide. If the data to be transmitted is a logical 1 (High), the
IR_TxD signal remains Low (0) for the full 16-clock period. If the data to be transmitted is
a logical 0, a 3-clock High (1) pulse is output following a 7-clock Low (0) period. Follow-
ing the 3-clock High pulse, a 6-clock Low pulse completes the full 16-clock data period.
Data transmission is illustrated in Figure 26. During data transmission, the IR receive
function should be disabled by clearing the IR_RxEN bit in the IR_CTL reg to 0. The SIR
data format uses half-duplex communication; the UART does not transmit data while the
receiver decoder is enabled.
Data is received from the IR transceiver via the IR_RxD signal and decoded by the IrDA
endec. This decoded data is passed from the endec to UART0. To enable receiver decode,
the IR_RxEN bit in the IR_CTL register must be set to 1. The SIR data format uses half-
duplex communication; therefore, the UART should not transmit data during normal oper-
ation while the receiver decoder is enabled.
Start Bit = 0
16-clock
period
3-clock
pulse
Data Bit 0 = 1
P R E L I M I N A R Y
Data Bit 1 = 0
Data Bit 2 = 1
Product Specification
Infrared Encoder/Decoder
Data Bit 3 = 1
eZ80F92/eZ80F93
127
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