EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 173

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
I
The I2C_CCR register is a Write Only register. The seven LSBs control the frequency at
which the I
is in MASTER mode. The Write Only I2C_CCR registers share the same I/O addresses as
the Read Only I2C_SR registers. See I
Table 91. I
The I
clock is f
In MASTER mode, the I
The use of two separately-programmable dividers allows the MASTER mode output fre-
quency to be set independently of the frequency at which the I
ture is particularly useful in multimaster systems because the frequency at which the I
bus is sampled must be at least 10 times the frequency of the fastest master on the bus to
ensure that START and STOP conditions are always detected. By using two programma-
ble clock divider stages, a high sampling frequency can be ensured while allowing the
MASTER mode output to be set to a lower frequency.
Bit
Reset
CPU Access
Note: W = Read only.
Bit
Position
7
[6:3]
M
[2:0]
N
f
f
2
SAMP
SCL
C Clock Control Register
2
=
C clocks are derived from the CPU system clock. The frequency of the CPU system
=
SCK
10 • (M + 1)(2)
2
2
C Clock Control Registers (I2C_CCR = 00CCh)
C bus is sampled and the frequency of the I
f
. The I
SCLK
2
N
f
SCLK
2
Value Description
0
0000–
1111
000–
111
C bus is sampled by the I
N
2
C clock output frequency on SCL (f
W
Reserved.
I
I
P R E L I M I N A R Y
7
0
2
2
C clock divider scalar value.
C clock divider exponent.
W
6
0
2
C Clock Control Registers (I2C_CCR = 00CCh).
W
5
0
2
C block at the frequency f
W
4
0
2
C clock line (SCL) when the I
W
3
0
SCL
2
C bus is sampled. This fea-
Product Specification
) is supplied by:
W
2
0
I2C Serial I/O Interface
eZ80F92/eZ80F93
SAMP
W
1
0
supplied by:
W
0
0
2
2
C
C
161