EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 167

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See I
Table 85. I
I
The I2C_XSAR register is used in conjunction with the I2C_SAR register to provide 10-
bit addressing of the I
bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}.
When the register receives an address starting with
the I
ACK after receiving the I2C_XSAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I
interrupt and goes into SLAVE mode.Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See I
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:1]
SLA
0
GCE
2
C Extended Slave Address Register
2
C recognizes that a 10-bit slave addressing mode is being selected. The I
2
C Slave Address Registers (I2C_SAR = 00C8h)
Value Description
00h–
7Fh
0
1
2
C when in SLAVE mode. The I2C_SAR value forms the lower 8
2
2
C Slave Address Registers (I2C_SAR = 00C8h).
C Extended Slave Address Registers (I2C_XSAR = 00C9h).
R/W
7-bit slave address or upper 2 bits,I2C_SAR[2:1], of address
when operating in 10-bit mode.
I
I
P R E L I M I N A R Y
7
0
2
2
C not enabled to recognize the General Call Address.
C enabled to recognize the General Call Address.
R/W
6
0
R/W
5
0
F7h
R/W
4
0
to
F0h
R/W
3
0
(I2C_SAR[7:3] = 11110b),
Product Specification
R/W
2
0
I2C Serial I/O Interface
eZ80F92/eZ80F93
2
C generates an
R/W
1
0
2
C sends an
R/W
0
0
155