EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 168

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Table 86. I
I
This register contains the data byte/slave address to be transmitted or the data byte just
received. In transmit mode, the most-significant bit of the byte is transmitted first. In
receive mode, the first bit received is placed in the most-significant bit of the register. After
each byte is transmitted, the I2C_DR register contains the byte that is present on the bus in
case a lost arbitration event occurs. See I
Table 87. I
I
The I2C_CTL register is a control register that is used to control the interrupts and the
master slave relationships on the I
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the
IFLG is set to 1. When IEN is cleared to 0, the interrupt line always remains Low.
When the Bus Enable bit (ENAB) is set to 0, the I
ignored and the I
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SLAX
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
DATA
2
2
C Data Register
C Control Register
2
2
C Extended Slave Address Registers (I2C_XSAR = 00C9h)
C Data Registers (I2C_DR = 00CAh)
2
C module does not respond to any address on the bus. When ENAB is
Value Description
00h–
FFh
Value Description
00h–
FFh
R/W
R/W
Least-significant 8 bits of the 10-bit extended slave address.
I
P R E L I M I N A R Y
7
0
7
0
2
C data byte.
2
R/W
R/W
C bus.
6
0
6
0
2
C Data Registers (I2C_DR = 00CAh).
R/W
R/W
5
0
5
0
2
C bus inputs SCLx and SDAx are
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
Product Specification
R/W
R/W
2
0
2
0
I2C Serial I/O Interface
eZ80F92/eZ80F93
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
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