EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 181
EZ80F920120MOD
Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog
Datasheets
1.EZ80F920120MOD.pdf
(269 pages)
2.EZ80F920120MOD.pdf
(4 pages)
3.EZ80F920120MOD.pdf
(2 pages)
Specifications of EZ80F920120MOD
Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
EZ80F920120MOD
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Figure 43.ZDI Single-Byte Data Read Timing
Figure 44.ZDI Block Data Read Timing
PS015308-0404
ZDA
ZCL
ZDA
ZCL
Operation of the eZ80F92 Device During ZDI Breakpoints
ZDI Address
ZDI Address
lsb of
ZDI Block Read
A Block Read operation is initiated the same as a single-byte Read; however, the ZDI
master continues to clock in the next byte from the ZDI slave as the ZDI slave continues to
output data. The ZDI register address counter increments with each Read. If the ZDI regis-
ter address reaches the end of the Read Only ZDI register address space (
stops incrementing. Figure 44 illustrates the ZDI’s Block Read timing.
lsb of
If the ZDI forces the CPU to BREAK, only the CPU suspends operation. The system
clock continues to operate and drive other peripherals. Those peripherals that can operate
autonomously from the CPU may continue to operate, if so enabled. For example, the
Watch-Dog Timer and Programmable Reload Timers continue to count during a ZDI
BREAK point.
A0
7
A0
7
Read
Read
8
8
Byte Separator
Byte Separator
Single-Bit
Single-Bit
0/1
9
0/1
9
of DATA
of DATA
msb
Byte 1
D7
msb
1
D7
1
D6
P R E L I M I N A R Y
2
D6
2
D5
3
D5
3
ZDI Data Byte
D4
ZDI Data Bytes
4
D1
7
of DATA
Byte 1
D3
5
D0
lsb
8
Byte Separator
Single-Bit
D2
0/1
6
9
of DATA
Byte 2
D1
msb
7
D7
1
Product Specification
of DATA
ZiLOG Debug Interface
D0
eZ80F92/eZ80F93
lsb
8
D6
2
START Signal
20h
End of Data
or New ZDI
1
), the address
9
1
9
169
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