EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 49

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Low-Power Modes
PS015308-0404
Overview
SLEEP Mode
HALT Mode
Caution:
The eZ80F92 device provides a range of power-saving features. The highest level of
power reduction is provided by SLEEP mode. The next level of power reduction is pro-
vided by the HALT instruction. The lowest level of power reduction is provided by the
clock peripheral power-down registers.
Execution of the CPU’s SLEEP instruction (SLP) places the eZ80F92 device into SLEEP
mode. In SLEEP mode, the operating characteristics are:
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The CPU can be brought out of SLEEP mode by any of the following operations:
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After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. Refer to the Reset section on page 34 for more information.
Execution of the CPU’s HALT instruction places the eZ80F92 device into HALT mode. In
HALT mode, the operating characteristics are:
The primary crystal oscillator is disabled
The system clock is disabled
The CPU is idle
The Program Counter (PC) stops incrementing
The 32 KHz crystal oscillator continues to operate and drive the Real-Time Clock and
the Watch-Dog Timer (if WDT is configured to operate from the 32 KHz oscillator)
A RESET via the external RESET pin driven Low
A RESET via a Real-Time Clock alarm
A RESET via execution of a Debug Reset command
During SLEEP mode, the CPU freezes the last address and drives the address
bus with this value. The GPIO ports remain as configured by the user. Prior to
entering SLEEP mode, the data bus is driven Low and the control signals
MREQ, CS3:0, INSTRD, BUSACK, IOREQ,RD, and WR are driven High.
P R E L I M I N A R Y
Product Specification
eZ80F92/eZ80F93
Low-Power Modes
37