EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 189

MODULE EZ80F92 512K 20MHZ

EZ80F920120MOD

Manufacturer Part Number
EZ80F920120MOD
Description
MODULE EZ80F92 512K 20MHZ
Manufacturer
Zilog

Specifications of EZ80F920120MOD

Module/board Type
Development Module
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1 MB
Interface Type
Cable
Maximum Clock Frequency
20 MHz
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
For Use With/related Products
eZ80F92
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3157
EZ80F920120MOD
PS015308-0404
ZDI Master Control Register
The ZDI Master Control register provides control of the eZ80F92 device. It is capable of
forcing a RESET and waking up the eZ80F92 device from the low-power modes (HALT
or SLEEP). See ZDI Master Control Register (ZDI_MASTER_CTL = 11h in ZDI Regis-
ter Write Address Spaces).
Table 98. ZDI Master Control Register
(ZDI_MASTER_CTL = 11h in ZDI Register Write Address Spaces)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
ZDI_RESET
[6:0]
Value
0
1
0000000 Reserved.
W
P R E L I M I N A R Y
7
0
Description
No action.
Initiate a RESET of the CPU. This bit is automatically
cleared at the end of the RESET event.
W
6
0
W
5
0
W
4
0
W
3
0
Product Specification
W
ZiLOG Debug Interface
2
0
eZ80F92/eZ80F93
W
1
0
W
0
0
177

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