EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 166

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
I
2
C Registers
Addressing
The processor interface provides access to six 8-bit registers: four Read/Write registers,
one Read Only register and two Write Only registers, as indicated in I
tions.
Table 84. I
Resetting the
Hardware reset.
I2C_SAR
I2C_SR
Software Reset.
Register (
IFLG bits of the
I
The I2C_SAR register provides the 7-bit address of the I
allows 10-bit addressing in conjunction with the
sla[6:0] is the 7-bit address of the I
this address after a START condition, it enters SLAVE mode. I2C_SAR[7] corresponds to
the first bit received from the I
When the register receives an address starting with
the I
ACK after receiving the I2C_SAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I
interrupt and goes into SLAVE mode.Then I2C_SAR[2:1] are used as the upper 2 bits for
Register
I2C_SAR
I2C_XSAR
I2C_DR
I2C_CTL
I2C_SR
I2C_CCR
I2C_SRR
2
C Slave Address Register
2
C recognizes that a 10-bit slave addressing mode is being selected. The I
register is set to
,
I2C_SRR
2
I2C_XSAR
C Register Descriptions
I
2
I2C_CTL
C
When the I
Perform a software reset by writing any value to the I
Registers
). A software reset sets the I
Description
Slave address register
Extended slave address register
Data byte register
Control register
Status register (Read Only)
Clock Control register (Write Only)
Software reset register (Write Only)
,
I2C_DR
F8h
register to 0.
P R E L I M I N A R Y
2
.
C is reset by a hardware reset of the eZ80F92 device, the
2
C bus.
and
2
C when in 7-bit SLAVE mode. When the I
I2C_CTL
registers are cleared to
2
C back to idle and the STP, STA, and
I2C_XSAR
F7h
to
2
C when in SLAVE mode and
F0h
register. I2C_SAR[7:1] =
(I2C_SAR[7:3] = 11110b),
Product Specification
2
I2C Serial I/O Interface
eZ80F92/eZ80F93
00h
C Register Descrip-
2
2
C Software Reset
C generates an
; while the
2
2
C sends an
C receives
154