EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 87

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Watch-Dog Timer Operation
Enabling and Disabling the WDT
The Watch-Dog Timer is disabled upon a RESET. To enable the WDT, the application pro-
gram must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the
WDT cannot be disabled without a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT—2
clock cycles. The WDT time-out period is defined by the WDT_PERIOD field of the
WDT_CTL register (WDT_CTL[1:0]). The approximate time-out periods for two differ-
ent WDT clock sources is listed in Watch-Dog Timer Approximate Time-Out Delays.
RESET Or NMI Generation
Upon a WDT time-out, the RST_FLAG bit in the WDT_CTL register is set to 1. In addi-
tion, the WDT can cause a RESET or send a nonmaskable interrupt (NMI) signal to the
CPU. The default operation is for the WDT to cause a RESET. It asserts/deasserts on the
rising edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the
source of the RESET event.
Clock Source
32.768 KHz Crystal Oscillator
32.768 KHz Crystal Oscillator
32.768 KHz Crystal Oscillator
32.768 KHz Crystal Oscillator
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
20 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
50 MHz System Clock
Note: *WDT time-out values should be sufficiently long to allow Flash
Table 26. Watch-Dog Timer Approximate Time-Out Delays
operations to complete.
P R E L I M I N A R Y
Divider Value
2
2
2
2
2
2
2
2
2
2
2
2
18
22
25
27
18
22
25
27
18
22
25
27
Time Out Delay
8.00 s
128 s
1024 s
4096 s
13.1 ms*
209.7 ms*
1.68 s
6.71 s
83.9 ms
5.2 ms
0.67 s
2.68 s
18
, 2
22
Product Specification
, 2
25
eZ80F92/eZ80F93
, and 2
Watch-Dog Timer
27
system
75