EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 165

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

PS015308-0404
Note:
is transmitted, the IFLG is set and the
the idle state. The AAK bit must be set to 1 before reentering SLAVE mode.
If no acknowledge is received after transmitting a byte, the IFLG is set and the
register contains
If a STOP condition is detected after an acknowledge bit, the I
Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master transmit-
ter.
The I
Write bit (lsb = 0) after a START condition. The I
sets the IFLG bit in the
60h
address
I
the transmission of an address, and the slave address and Write bit (or the general call
address if the CGE bit in the
the
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the AAK bit in the
SDA) is transmitted and the IFLG bit is set after each byte is received. The
ter contains the status code
general call address. The received data byte can be read from the
IFLG bit must be cleared to allow the transfer to continue. If a STOP condition or a
repeated START condition is detected after the acknowledge bit, the IFLG bit is set and
the
If the AAK bit is cleared to 0 during a transfer, the I
(High level on SDA) after the next byte is received, and set the IFLG bit. The
ister contains the status code
general call address. The I
2
C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during
I2C_SR
I2C_SR
. The I
2
C enters SLAVE RECEIVE mode when it receives its own slave address and a
When the I
I2C_SAR
received but no interrupt is generated. IFLG is not set and the status does not
change. The I
received. The I
00h
2
C also enters SLAVE RECEIVE mode when it receives the general call
register is
register contains status code
(if the GCE bit in the
C0h
register), it transmits an acknowledge after the first address byte is
2
C contains a 10-bit slave address (signified by
2
. The I
I2C_CTL register
C generates an interrupt only after the second address byte is
2
68h
C sets the IFLG bit and loads the status code as described above.
I2C_CTL
2
C returns to the idle state when the IFLG bit is cleared to 0.
if the slave address is received or
80h
2
P R E L I M I N A R Y
C then returns to the idle state.
I2C_SAR
88h
or
register and the
or
I2C_SAR
90h
98h
I2C_SR
register is set to 1) are received. The status code in
if SLAVE RECEIVE mode is entered with the
is set to 1 then an acknowledge bit (Low level on
A0h
if SLAVE RECEIVE mode is entered with the
register is set). The status code is then
.
register contains
I2C_SR
2
C transmits an acknowledge bit and
2
C transmits a not-acknowledge bit
register contains the status code
78h
2
C8h
C returns to the idle state.
Product Specification
I2C_DR
F0h–F7h
if the general call
and the I
I2C Serial I/O Interface
eZ80F92/eZ80F93
register and the
I2C_SR
in the
2
I2C_SR
C returns to
I2C_SR
70h
regis-
reg-
.
153