EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 202

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

On-Chip Instrumentation
PS015308-0404
Introduction to On-Chip Instrumentation
OCI Activation
On-Chip Instrumentation
features. The OCI provides run control, memory and register visibility, complex break-
points, and trace history features.
The OCI employs all of the functions of the ZiLOG Debug Interface (ZDI) as described in
the ZDI section. It also adds the following debug features:
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There are four sections to the OCI:
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OCI features clock initialization circuitry so that external debug hardware can be detected
during power-up. The external debugger must drive the OCI clock pin (TCK) Low at least
two system clock cycles prior to the end of the RESET to activate the OCI block. If TCK
is High at the end of the RESET, the OCI block shuts down so that it does not draw power
in normal product operation. When the OCI is shut down, ZDI is enabled directly and can
1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions, Inc.
2. The eZ80F92 does not contain the boundary scan register required for 1149.1 compliance.
Control via a 4-pin JTAG port that conforms to IEEE Standard 1149.1 (Test Access
Port and Boundary Scan Architecture)
Complex break point trigger functions
Break point enhancements, such as the ability to:
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Trace history buffer
Software break point instruction
JTAG interface
ZDI debug control
Trace buffer memory
Complex triggers
Define two break point addresses that form a range
Break on masked data values
Start or stop trace
Assert a trigger output signal
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(OCI™) for the eZ80
P R E L I M I N A R Y
2
®
CPU core enables powerful debugging
Product Specification
On-Chip Instrumentation
eZ80F92/eZ80F93
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