EZ80F920120MOD Zilog, EZ80F920120MOD Datasheet - Page 31

• Manufacturer Part Number: EZ80F920120MOD
• Description: MODULE EZ80F92 512K 20MHZ
• Manufacturer: Zilog

Specifications of EZ80F920120MOD

• Module/board Type: Development Module
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 MB
• Interface Type: Cable
• Maximum Clock Frequency: 20 MHz
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: 0 C
• For Use With/related Products: eZ80F92
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3157; EZ80F920120MOD

Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)
PS015308-0404
Pin #
92
93
94
95
Symbol
PB4
T4_OUT
PB5
T5_OUT
PB6
MISO
PB7
MOSI
Function
GPIO Port B
Timer 4 Out
GPIO Port B
Timer 5 Out
GPIO Port B
Master In,
Slave Out
GPIO Port B
Master Out,
Slave In
Signal Direction
Bidirectional
Output
Bidirectional
Output
Bidirectional
Bidirectional
Bidirectional
Bidirectional
P R E L I M I N A R Y
Description
This pin can be used for general-purpose I/
O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each Port
B pin, when programmed as output, can be
selected to be an open-drain or open-
source output.
Programmable Reload Timer 4 timer-out
signal. This signal is multiplexed with PB4.
This pin can be used for general-purpose I/
O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each Port
B pin, when programmed as output, can be
selected to be an open-drain or open-
source output.
Programmable Reload Timer 5 timer-out
signal. This signal is multiplexed with PB5.
This pin can be used for general-purpose I/
O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each Port
B pin, when programmed as output, can be
selected to be an open-drain or open-
source output.
The MISO line is configured as an input
when the CPU is an SPI master device and
as an output when CPU is an SPI slave
device. This signal is multiplexed with PB6.
This pin can be used for general-purpose I/
O. It can be individually programmed as
input or output and can also be used
individually as an interrupt input. Each Port
B pin, when programmed as output, can be
selected to be an open-drain or open-
source output.
The MOSI line is configured as an output
when the CPU is an SPI master device and
as an input when the CPU is an SPI slave
device. This signal is multiplexed with PB7.
Product Specification
eZ80F92/eZ80F93
Architectural Overview
19